1. Field of the Invention
This invention relates to a level shifting circuit constructed by MOS transistors, and more particularly, to a level shifting circuit in which the amplitude of an output signal is prevented from being fully swung to the power source voltage.
2. Description of the Related Art
FIG. 1 shows the construction of a conventional level shifting circuit for shifting the amplitude of a CMOS logic level signal to a lower level. For example, this type of level shifting circuit is disclosed in FIG. 1 of Published Unexamined Japanese Patent Application No. 55-146965. In the level shifting circuit of FIG. 1, the drain-source path of an N-channel MOS transistor N1 is connected between a power source node applied with a positive-side power source voltage Vcc and an output terminal and the drain-source path of an N-channel MOS transistor N2 is connected between the output terminal and a power source node applied with a ground voltage Vss. The gate of the N-channel MOS transistor N2 is supplied with an input signal IN and the gate of the N-channel MOS transistor N1 is supplied with a signal obtained by inverting the input signal IN by means of a CMOS inverter INV1. Both of the N-channel MOS transistors N1 and N2 are of enhancement type.
When an input signal IN of "H" level is input to the above level shifting circuit, the MOS transistor N1 is turned off and the MOS transistor N2 is turned on so that an output signal OUT will be set to an "L" level. The "L" level of the output signal OUT obtained at this time is a ground level. When the input signal IN of "L" level is input, the MOS transistor N1 is turned on and the MOS transistor N2 is turned off so that the output signal OUT will be set to an "H" level. At this time, the "H" level of the output signal OUT is not raised to the power source voltage Vcc and is set to a level "Vcc-VthN1" obtained by subtracting the threshold voltage VthN1 of the N-channel MOS transistor N1 from the power source voltage Vcc. Thus, in the level shifting circuit of FIG. 1, the "H" level side is shifted to a lower level.
FIG. 2 shows a general layout obtained when the circuit of FIG. 1 is set in a package as a semiconductor integrated circuit. A semiconductor integrated circuit (chip) 12 is mounted on a bed 11 of a lead frame by die bonding. P-channel and N-channel MOS transistors 13 and 14 constructing the inverter INV1, an internal metal wiring 15 for supplying the power source voltage Vcc to the MOS transistors N1 and 13, an internal metal wiring 16 for supplying the ground voltage Vss to the MOS transistors N2 and 14, bonding pads 17-1 to 17-4 and the like are formed in the chip 12. The bonding pads 17-1 to 17-4 are respectively connected to inner leads 19-1 to 19-4 of the lead frame via boding wires 18-1 to 18-4.
As shown in FIG. 2, the drain of the MOS transistor N1 is connected to the source of the P-channel MOS transistor 13 of the inverter INV1 via the wiring 15 in the semiconductor integrated circuit, and therefore, the potentials of the drain of the MOS transistor N1 and the source of the MOS transistor 13 are set substantially equal to each other. As a result, a variation in the potential occurring in one of the drain and source gives an influence to the other of the drain and source. Then, the following problem occurs in the conventional circuit.
Assume now that the output signal voltage VOUT is set at the Vss level (which is hereinafter referred to as an "L" level) in the initial condition, that is, when the input signal voltage VIN is set at the Vcc level (which is hereinafter referred to as an "H" level). At this time, the potential at the output node of the inverter INV1 is set at the "L" level, the MOS transistor N1 is set in the OFF state and the MOS transistor N2 is set in the ON state. Therefore, the output signal VOUT is set to the "L" level.
When the voltage VIN is switched from the "H" level to the "L" level, the conduction state of the MOS transistor N1 is changed from the OFF state to the ON state and the conduction state of the MOS transistor N2 is changed from the ON state to the OFF state. AS a result, a current for driving a load (not shown) connected to the output terminal flows into the current path of the MOS transistor N1. At this time, a voltage variation of L(di/dt) occurs in the drain of the MOS transistor N1 as shown in FIG. 3 by the current variation rate di/dt and an inductance component (parasitic inductance components associated with the internal metal wiring 15, bonding wire 18-1, inner lead 19-1 and the like) L associated with the Vcc line (internal metal wiring 15). That is, a potential bounce occurs in the Vcc line. The potential bounce is transmitted to the output node of the inverter INV1 via the internal metal wiring 15 so that a bounce may occur in the gate potential of the MOS transistor N1.
When the gate potential bounce is not taken into consideration, the output signal voltage VOUT may be raised to "Vcc-VthN1" as describe before and then set to a constant level. The voltage is indicated by broken lines in FIG. 3. However, when the gate potential bounce is taken into consideration, the output signal voltage VOUT set when the output signal OUT is at "H" level becomes larger than "Vcc-VthN1" by an amount .DELTA. under the influence of a potential bounce causing the power source voltage Vcc to exceed the Vcc level. At this time, even if the potential bounce in the power source voltage Vcc becomes lower than Vcc, the output level will not be lowered. This is because the relation "Vcc-VOUT&lt;VthN1" is set up. Thus, if the power source voltage Vcc is set to be higher than the Vcc level to which the power source voltage Vcc will be originally set and VOUT is raised by an amount .DELTA., VOUT is kept set at a raised level even after the power source voltage Vcc is returned to the original voltage level.
If a large number of level shifting circuits having the same construction as the above shifting circuit are formed in a semiconductor integrated circuit, the number of circuits whose outputs are switched increases and L(di/dt) becomes extremely large, the output amplitude becomes larger and may sometimes reach Vcc. Then, a problem that the level-down operation which is the initial purpose cannot be attained occurs. Thus, in the conventional level shifting circuit, there occurs a problem that the potential bounce occurs in the power source line and the upper limit of the output amplitude level cannot be controlled.
The level shifting circuit of FIG. 1 is constructed by the N-channel MOS transistors and the "H" level of the output amplitude is shifted down to "Vcc-VthN1", but the same problem occurs when the level shifting circuit is constructed by P-channel MOS transistors and the "L" level of the output amplitude is shifted up to .vertline.VthP.vertline. (.vertline.VthP.vertline. is the absolute value of the threshold voltage of the P-channel MOS transistor). That is, in this case, a problem of undershoot occurs when the output signal is switched from the "H" level to the "L" level, thereby causing a bounce to occur in the ground potential.